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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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rev.3.00, oct.02. 2003, page 1 of 9 hd74alvch162244 16-bit buffers / drivers with 3-state outputs rej03d0052-0300z (previous ade-205-173a(z)) rev.3.00 oct.02.2003 description the hd74alvch162244 is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus orient ed receivers and transmitters. the device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. it provides true outputs and symmetrical active-low output-enable ( oe ) inputs. to ensure the high impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. all outputs, which are designed to sink up to 12 ma, include 26 ? resistors to reduce overshoot and undershoot. ? v cc = 2.3 v to 3.6 v ? typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) ? typical v oh undershoot > 2.0 v (@v cc = 3.3 v, ta = 25c) ? high output current 12 ma (@v cc = 3.0 v) ? bus hold on data inputs eliminates the need for external pullup / pulldown resistors ? all outputs have equivalent 26 ? series resistors, so no ex ternal resistors are required.
hd74alvch162244 rev.3.00, oct.02. 2003, page 2 of 9 function table inputs oe a output y lhh lll hxz h : high level l : low level x : immaterial z : high impedance
hd74alvch162244 rev.3.00, oct.02. 2003, page 3 of 9 pin arrangement (top view) 1 2 3 4 5 6 7 8 9 10 v cc 1 oe 1y1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1y2 gnd 1y3 1y4 2y1 2y2 gnd 2y3 2y4 3y1 3y2 gnd 3y3 3y4 4y1 4y2 gnd 4y3 4y4 4 oe v cc 3 oe 4a4 4a3 gnd 4a2 4a1 3a4 3a3 gnd 3a2 3a1 2a4 2a3 gnd 2a2 2a1 1a4 1a3 1a2 2 oe gnd 1a1 v cc v cc
hd74alvch162244 rev.3.00, oct.02. 2003, page 4 of 9 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc ?0.5 to 4.6 v input voltage *1 v i ?0.5 to 4.6 v output voltage *1, 2 v o ?0.5 to v cc +0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 50 ma v o = 0 to v cc v cc , gnd current / pin i cc or i gnd 100 ma maximum power dissipation at ta = 55c (in still air) *3 p t 0.85 w tssop storage temperature tstg ?65 to 150 c notes: stresses beyond those listed under ?absolut e maximum ratings? may cause permanent damage to the device. these are stress ratings only, and f unctional operation of t he device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. this value is limited to 4.6 v maximum. 3. the maximum package power dissipation is calc ulated using a junction temperature of 150c and a board trace length of 750 mils. recommended operating conditions item symbol min max unit conditions supply voltage v cc 2.3 3.6 v input voltage v i 0v cc v output voltage v o 0v cc v high level output current i oh ??6mav cc = 2.3 v ??8 v cc = 2.7 v ? ?12 v cc = 3.0 v low level output current i ol ?6 mav cc = 2.3 v ?8 v cc = 2.7 v ?12 v cc = 3.0 v input transition rise or fall rate ? t / ? v 0 10 ns / v operating temperature ta ?40 85 c note: unused control inputs must be held hi gh or low to prevent them from floating.
hd74alvch162244 rev.3.00, oct.02. 2003, page 5 of 9 logic diagram 1 oe 1 47 46 44 43 1a1 1a2 1a3 1a4 2 3 5 6 1y1 1y2 1y3 1y4 2 oe 48 41 40 38 37 2a1 2a2 2a3 2a4 8 9 11 12 2y1 2y2 2y3 2y4 3 oe 25 36 35 33 32 3a1 3a2 3a3 3a4 13 14 16 17 3y1 3y2 3y3 3y4 4 oe 24 30 29 27 26 4a1 4a2 4a3 4a4 19 20 22 23 4y1 4y2 4y3 4y4
hd74alvch162244 rev.3.00, oct.02. 2003, page 6 of 9 electrical characteristics (ta = ?40 to 85c) item symbol v cc (v) min max unit test conditions 2.3 to 2.7 1.7 ? v ih 2.7 to 3.6 2.0 ? 2.3 to 2.7 ? 0.7 input voltage v il 2.7 to 3.6 ? 0.8 v 2.3 to 3.6 v cc ?0.2 ? i oh = ?100 a 2.3 1.9 ? i oh = ?4 ma, v ih = 1.7 v 2.3 1.7 ? i oh = ?6 ma, v ih = 1.7 v 3.0 2.4 ? i oh = ?6 ma, v ih = 2.0 v 2.7 2.0 ? i oh = ?8 ma, v ih = 2.0 v v oh 3.0 2.0 ? i oh = ?12 ma, v ih = 2.0 v 2.3 to 3.6 ? 0.2 i ol = 100 a 2.3 ? 0.4 i ol = 4 ma, v il = 0.7 v 2.3 ? 0.55 i ol = 6 ma, v il = 0.7 v 3.0 ? 0.55 i ol = 6 ma, v il = 0.8 v 2.7 ? 0.6 i ol = 8 ma, v il = 0.8 v output voltage v ol 3.0 ? 0.8 v i ol = 12 ma, v il = 0.8 v i in 3.6 ? 5 v in = v cc or gnd 2.3 45 ? v in = 0.7 v 2.3 ?45 ? v in = 1.7 v 3.0 75 ? v in = 0.8 v 3.0 ?75 ? v in = 2.0 v input current i in (hold) 3.6 ? 500 a v in = 0 to 3.6 v *1 off state output current i oz 3.6 ? 10 av out = v cc or gnd i cc 3.6 ? 40 av in = v cc or gnd quiescent supply current ? i cc 3.0 to 3.6 ? 750 av in = one input at (v cc ?0.6) v, other inputs at v cc or gnd notes: 1. this is the bus hold maximum dynamic curre nt required to switch the input from one state to another.
hd74alvch162244 rev.3.00, oct.02. 2003, page 7 of 9 switching characteristics (cont) (ta = ?40 to 85c) item symbol v cc (v) min typ max unit from (input) to (output) 2.50.2 1.0 ? 4.9 2.7??4.7 propagation delay time t plh t phl 3.30.3 1.0 ? 4.2 ns a y 2.50.2 1.0 ? 6.8 2.7??6.7 output enable time t zh t zl 3.30.3 1.0 ? 5.6 ns oe y 2.50.2 1.0 ? 6.3 2.7??5.7 output disable time t hz t lz 3.30.3 1.0 ? 5.5 ns oe y input capacitance c in 3.3 ? 3.0 ? control inputs 3.3 ? 6.0 ? pf data inputs output capacitance c o 3.3 ? 7.0 ? pf outputs test circuit 500 ? c = 50 pf l 500 ? s1 *1 see under table gnd open load circuit for outputs symbol t / t plh phl open open gnd cc 2 v 6.0 v t / t zh hz t / t zl lz gnd vcc=2.7v, 3.30.3v vcc=2.50.2v note: 1. c l includes probe and jig capacitance.
hd74alvch162244 rev.3.00, oct.02. 2003, page 8 of 9 waveforms ? 1 t plh t phl v oh v ol gnd v ih v ref v ref v ref v ref input output 10 % 90 % t r f t 10 % 90 % waveforms ? 2 v ref1 v ref2 t zl t lz t zh t hz v oh v ol v cc v +0.15 v ol v ?0.15 v oh v +0.3 v ol v ?0.3 v oh v cc cc waveform - a output control waveform - b gnd v ih test v ih v ref v ref1 v ref2 1/2 v 1.5 v 2.7 v v oh1 v ol1 3.0 v gnd gnd vcc=2.7v, 3.30.3v vcc=2.50.2v 10 % 10 % 90 % 90 % t r t f v ref v ref v ref v ref v oh1 v ol1 notes: 1. all input pulses are supplied by genera tors having the following characteristics : prr 10 mhz, zo = 50 ? , t r 2.0 ns, t f 2.0 ns. (v cc = 2.5 0.2 v) prr 10 mhz, zo = 50 ? , t r 2.5 ns, t f 2.5 ns. (v cc = 2.7 v, 3.3 0.3 v) 2. waveform ? a is for an output with internal co nditions such that the output is low except when disabled by the output control. 3. waveform ? b is for an output with internal co nditions such that t he output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement.
hd74alvch162244 rev.3.00, oct.02. 2003, page 9 of 9 package dimensions package code jedec jeita mass (reference value) ttp-48dbv ? ? 0.20 g *ni/pd/au plating 0.08 m 0.10 *0.15 0.05 8.10 0.20 0.50 0.1 0.65 max 124 25 48 12.5 6.10 0? ? 8? 0.50 1.20 max 0.10 0.05 12.7 max 1.0 *0.19 0.05 as of january, 2003 unit: mm
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